Overview of ARM64 ABI conventions | Microsoft Learn
https://learn.microsoft.com/en-us/cpp/build/arm64-windows-abi-conventions?view=msvc-170
OverviewDefinitionsBase requirementsEndiannessAlignmentInteger registersFloating-point/SIMD registersSystem registersFloating-point exceptionsParameter passingThe AArch64 architecture supports 32 integer registers:Each register may be accessed as a full 64-bit value (via x0-x30) or as a 32-bit value (via w0-w30). 32-bit operations zero-extend their results up to 64 bits.See the Parameter passing section for details on the use of the parameter registers.Unlike AArch32, the program counter (PC) and the stack pointer (SP) aren't indexed registers. They're limited in how they may be accessed. Also note that there's no x31 register. That encoding is used for special purposes.See more on learn.microsoft.comExplore further The AArch64 architecture supports 32 integer registers:Each register may be accessed as a full 64-bit value (via x0-x30) or as a 32-bit value (via w0-w30). 32-bit operations zero-extend their results up to 64 bits. See the Parameter passing section for details on the use of the parameter registers.Unlike AArch32, the program counter (PC) and the stack pointer (SP) aren't indexed registers. They're limited in how they may be accessed. Also note that there's no x31 register. That encoding is used for special purposes.
The AArch64 architecture supports 32 integer registers:Each register may be accessed as a full 64-bit value (via x0-x30) or as a 32-bit value (via w0-w30). 32-bit operations zero-extend their results up to 64 bits.
See the Parameter passing section for details on the use of the parameter registers.Unlike AArch32, the program counter (PC) and the stack pointer (SP) aren't indexed registers. They're limited in how they may be accessed. Also note that there's no x31 register. That encoding is used for special purposes.
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